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application note r01an0585ej0202 rev.2.02 p age 1 of 22 feb 14, 2014 RX62N group and rx621 group 16 - bit sdram connection and access examples i ntroduction this application note presents methods for connecting and accessing 16 - bit sdram to RX62N and rx621 group microcontrollers. target devices r x62n group and rx621 group this application note also applies to rx family microcontrollers that have the same i/o registers (peripheral module control registers) as the RX62N and rx621 group microcontrollers. however, since there have been additions to ce rtain functions, please check the manuals carefully for differences. when applying this application note to other microcontrollers, the information presented in this application note must be modified to match the specifications of the microcontroller used and the resulting system tested thoroughly. contents 1. specifications .................................................................................................................................... 2 2. operation confirmation conditions ................................................................................................... 3 3. usage notes ...................................................................................................................................... 3 4. operating d escription ........................................................................................................................ 4 5. software documentation ................................................................................................................. 12 6. reference documents ..................................................................................................................... 21 r01an0585ej0202 rev.2.02 feb 14, 2014
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 2 of 22 feb 14, 2014 1. specifications the sdram interface included in the RX62N and rx621 group microcontrollers allows the direct connection of up to 128 mb (1024 mbits) of sdram. this interface supports sdram with a cas latency of 1 to 3 cycles. this application note uses a micron technology 128 mbit sdram (the 2 mword 16 bit 4 bank mt48lc8m16a2p - 75), and connects to it over a 16 - bit bus. figure 1 shows a sample dram connection diagram and table 1 lists the sdram specifications. RX62N a12-a1 d15-d0 sdcs# ras# cas# we# dqm0 cke sdclk a11-a0 dq15-dq0 cs# ras# cas# we# dqml cke clk ba1-0 a14-a13 2 12 16 sdram mt48lc8m16a2p-75 2m-word 16bit 4bank dqm1 dqmh figure 1 16- bit sdram connection table 1 sdram specifications item symbol description catalog number ? mt48lc 8 m 16a 2p - 75 (micron technology, inc) structure ? 2 mwords 16 bits 4 banks capacity ? 128 mb row address lines ? a11 - a 0 column address lines ? a 8 - a 0 auto refresh interval ? 4096 refresh cycles every 64 ms cas latency ? 2/ 3 initialization auto refresh count ? 2 times auto refresh period ( trfc ) 66 ns ( min ) write recovery period ( twr ) 28.33 ns ( min ) precharge command period ( trp ) 2 0 ns ( min ) period from active command to precharge command ( tras ) 44 ns ( min ) delay time from active command to read/write command ( trcd ) 2 0 ns ( min )
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 3 of 22 feb 14, 2014 2. operation confirmation conditions the sample code accompanying this application note has been run and confirmed under the conditions below. table 2 operation confirmation conditions item contents device RX62N ( r5f562n8bdbg ) boad rsk RX62N (r0k5562n0 s000be ) power supply voltage 3.3 v ( supplied from the e1. ) input clock 12 mhz (iclk = 96 mhz, pclk = 48 mhz, bclk/sdclk = 48 mhz) operating t emperature room temperature hew version 4. 0 9 .0 1 .00 7 toolchain rx standard toolchain (v.1 . 2 . 1 .0 ) debugger/ emulator e1 emulator debugger component rx e1/ e20 system v.1. 0 3 .00.000 3. usage notes bus see the user's manual: hardware listed in section 6, reference documents.
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 4 of 22 feb 14, 2014 4. operating description 4.1 sdram initialization sequence setup before accessing the sdram used, it is necessary to initialize that sdram. this initialization should be performed once after a res et. the initialization sequence must observe the initialization auto refresh interval, initialization auto refresh count, and initialization precharge cycle stipulated in the sdram's data sheet. the methods for determining the setting values are shown belo w. table 3 lists the setting values. (1) initialization auto refresh interval since the auto refresh interval (trfc) for the sdram used in this application note is 66 ns (minimum), the sdramc initialization auto refresh interval must meet the following co ndition. 66 ns (min) initialization auto refresh interval also, since the sdram clock (sdclk) setting used in this application note is 48 mhz, the sdclk period will be 1/48 mhz. therefore, 66 ns (min)/(1/48 mhz) = 3.17 cycles accordingly, an initialization auto refresh period of at least 4 cycles is required. therefore the initialization auto refresh period bits (arfi[3:0]) are set to 0001b. (2) initialization auto refresh count the sdram used in this application note requires that the initia lization auto refresh operation be performed twice. therefore the initialization auto refresh count bits (arfc[3:0]) are set to 0010b. (3) initialization precharge cycle since the precharge command period (trp) for the sdram used in this application note is 20 ns (minimum), the sdramc initialization precharge cycle count must meet the following condition. 20 ns (min) initialization precharge cycle count since 20 ns/(1/48 mhz) = 0.96 cycles, at least one sdram initialization precharge cycle is required. however, since fewer than 3 cycles cannot be set according to the RX62N sdramc specifications, the set value will be 3 cycles. therefore the initialization precharge cycle count setting bits (prc[2:0]) are set to 000b.
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 5 of 22 feb 14, 2014 table 3 sdram initialization auto refresh control register (sdir) bit name setting value function initialization auto refresh period bits (arfi[3:0]) 0001b 4 cycles initialization auto refresh count bits (arfc[3:0]) 0010b 2 times initialization precharge cycle count setting bits (prc[2:0]) 000b 3 cycles pra dsl rfa sdclk sdram command initialization precharge cycle dsl dsl dsl dsl rfa dsl dsl dsl sdir.prc: "000" = 3 cycles sdir.arfi: "0001" = 4 cycles sdir.arfc: "0010" = 2 times dsl: device deselect command rfa: auto refresh command pra: all bank precharge command initialization auto refresh cycle initialization auto refresh cycle figure 2 initialization sequence timing
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 6 of 22 feb 14, 2014 4.2 sdram mode register settings after sdram initialization, the sdram mode register must be set. the mode must be set once and only once after initialization. with the RX62N sdramc, the sdram mode register can be written automatically by setting the sdram mode register (smod). table 4 lists the setting values. (1) mode register the RX62N sdramc operates w ith a burst length of 1. operation is not guaranteed if a burst length other then 1 is set. this application note uses a burst length of 1, a column latency of 3 cycles, and single access mode. table 4 sdram mode register (sdmod) bit name setting value fu nction mode register setting bits (mr[14:0]) 230h a burst length of 1, a column latency of 3 cycles, and single access mode. sdclk mode register setting cycle mrs dsl sdram command dsl a address bus dsl: device deselect mrs: mode register setting command 3 cycles (fixed) figure 3 sdram mode register setting timing
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 7 of 22 feb 14, 2014 4.3 auto refresh settings in this application note, auto refresh is performed for the sdram used. auto refresh must be performed while observing the auto refresh required interval and auto refresh release cycles as stipulated in the sdram data sheet. th e methods for determining the setting values are shown below. table 5 lists the setting values used. (1) auto refresh required interval the auto refresh required interval can be determined with the following formula. rfc (auto refresh required interval setting) = (auto refresh required interval/sdclk period) ? 1 since the sdram used in this application note requires that 4096 auto refresh operations be performed every 64 ms, the auto refresh interval can be determined from the following formula. auto ref resh required interval = 64 ms/4096 = 15.62 s also, since the sdram clock (sdclk) frequency used in the application note is 48 mhz, the sdclk period is 1/48 mhz. therefore, rfc (auto refresh required interval setting) = (15.62 s/(1/48 mhz)) ? 1 = 749 = 2edh therefore the auto refresh required interval setting bits (rfc[11:0]) are set to 2edh. (2) auto refresh release cycle since the auto refresh period (trfc) for the sdram used in this application note is 66 ns (minimum), the auto refresh releas e cycle must meet the following condition. 66 ns (min) auto refresh release cycle since this means that this cycle will be 66 ns/(1/48 mhz) = 3.17 cycles an auto refresh release cycle count of at least 4 cycles is required. therefore the auto refresh release cycle setting bits (refw[3:0]) are set to 0011b. table 5 sdram auto refresh control register (sdrfcr) bit name setting value function a uto refresh required interval setting bits ( rfc[11: 0]) 02edh 749 cycles auto refresh cycle/auto refresh release cycle setting bits (refw[3:0]) 0011b 4 cycles
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 8 of 22 feb 14, 2014 rfa dsl dsl sdram command auto refresh cycle sdclk dsl rfa dsl dsl auto refresh cycle dsl auto refresh interval dsl: device deselect command rfa: auto refresh command refw: "0011" = 4 cycles refc: "02edh" = 749 cycles figure 4 auto refresh timing
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 9 of 22 feb 14, 2014 4.4 sdram timing settings in this application note, the access timings are set to match the specifications of the sdram used. it is necessary to observe the access timings stipulated in the sdram data sheet when accessing sdram. the methods for determining the setting values are shown below. table 6 lists the setting values used. (1) s dramc column latency setting since the sdram used in this application note can be operated with a cas latency of from 1 to 3 cycles, in this application note, the cas latency is set to 3 cycles. therefore the sdramc column latency setting bits (cl[2:0]) ar e set to 011b. (2) write recovery period setting since the sdram used in this application note has a write recovery period (twr) of 28.3 ns (minimum), the sdramc write recovery period is set to meet the following condition 28.3 ns (min) write recovery period since 28.3 ns/(1/48 mhz) = 1.36 cycles, a write recovery period of at least 2 cycles is required. therefore the write recovery period setting bit (wr) is set to 1b. (3) row precharge period setting since the sdram used in this ap plication note has a row precharge period (trp) of 20 ns (minimum), the sdramc row precharge period must meet the following condition. 20 ns (min) row precharge period since 20 ns/(1/48 mhz) = 0.96 cycles, a row precharge period of at least 1 cycle is required. therefore the row precharge period setting bits (rp[2:0]) are set to 000b. (4) row active period setting since the sdram used in this application note has a period (tras) from an active command to a precharge command of 44 ns (minimum), the sd ramc row active period will be: 44 ns (min) row active period since 44 ns/(1/48 mhz) = 2.11 cycles, a row active period of at least 3 cycles is required. therefore the row active period setting bits (ras[2:0]) are set to 010b. note that the sdramc row active period setting bits must be set so that the following stipulation is observed. row active period row column latency + sdrac column latency
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 10 of 22 feb 14, 2014 (5) row column latency setting since the sdram used in this application note has a delay time (trcd) of 20 ns (minimum) from the point an active command is issued until a read/write command is issued, the sdramc row column latency will be: 20 ns (min) row column latency since 20 ns/(1/48 mhz) = 0.96 cycles, a row column latency of at least 1 cycle must be set. to observe stipulations on the sdramc row active period setting bits, the following condition must be observed. row active period row column latency + sdramc column latency in this application note, the row active period is set to 3 cycles and the sdramc column latency is also set to 3 cycles. here, we determined the row column latency setting cycles using the above formula. row column latency setting cycle count (3 cycles) ? (3 cycles) 0 cycles however, since the row column latency setting bits (rcd[1:0]) cannot be set to 0 cycles, in this application note, this field is set to 1 cycle, or 00b. table 6 sdram timing register (sdtr) bit name setting value function sdramc column latency setting bits ( cl[2: 0 ] ) 011 b 3 cycles write recovery period setting bit ( wr ) 1 b 2 cycles row precharge period setting bits ( rp[2: 0 ] ) 000b 1 cycle row active period setting bits ( ras[2: 0 ] ) 0 1 0b 3 cycles row column latency setting bits ( rcd[1: 0 ] ) 00 b 1 cycle act sdram command pra data bus sdclk act: bank active command rd: read command pra: all banks precharge command dsl: device deselect command dsl d0 rcd: 1 cycle cl: 3 cycles rp: 1 cycle ras: 3 cycles single read rd figure 5 read timing
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 11 of 22 feb 14, 2014 single write act sdram command pra d0 data bus sdclk act: bank active command wri: write command pra: all banks precharge command dsl: device deselect command wri dsl rcd: 1 cycle wr: 2 cycles ras: 3 cycles pr: 1 cycle figure 6 write timing
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 12 of 22 feb 14, 2014 5. software documentation 5.1 symbolic constants table 7 symbolic constants constant name setting value contents function used sdram_top 0x08000000 sdram (32bit) sdram (32 bits) start address main sdram_end 0x09000000 sdram (32bit) sdram (32 bits) end address main 5.2 ram variables table 8 ram variables type variable name contents function used u nsigned long sdram_adr sdram (32 bits) address pointer main u nsigned long sdram_data sdram (32 bits) data variable main u nsigned long sdram_cmp_data sdram (32 bits) comparison data main 5.3 functions table 9 functions function name outline poweron_reset_pc initialization function sets intb, fpsw, and psw, changes the processor mode, and calls the function main(). m ain main function calls the function init(), performs program operations (reads and writes to sdram), and calls the function err(). i nit mcu initialization function sets up various registers. e rr error function performs sdram data compare check error handling.
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 13 of 22 feb 14, 2014 5.4 registers used the tables below lists the registers used by this application note. note that the setting values shown are the ones used in this application note and differ from the initial values. (1) clock generation circuit system clock control register (sckcr) bits: 32, address: 0008 0020h bit symbol setting name function r/w b11 - b8 pck[3: 0 ] 000 1 peripheral module clock selection bits 000 1 : (2) operating mode system control register 0 (syscr0) bits: 8 , address: 0008 00 06 h bit symbol setting name function r/w b 0 rome 1 internal rom enable bit 1: internal rom enabled r/w b1 exbe 1 external bus enable bit 1: external bus enabled r/w b15 - b8 key[7:0] 5ah syscr0 key code 5ah: syscr0 register write enabled r/w
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 14 of 22 feb 14, 2014 (3) i/o ports port function register 3 (pf3bus) bits: 8 , address: 000 8 c1 0 3h bit symbol setting name function r/w b 0 a16e 0 address a16 output enable bit 0: a16 output disabled r/w b 1 a17e 0 address a1 7 output enable bit 0: a1 7 output disabled r/w b 2 a18e 0 address a1 8 output enable bit 0: a1 8 output disabled r/w b 3 a19e 0 address a1 9 output enable bit 0: a1 9 output disabled r/w b 4 a20e 0 address a 20 output enable bit 0: a 20 output disabled r/w b 5 a21e 0 address a 21 output enable bit 0: a 21 output disabled r/w b 6 a22e 0 address a 22 output enable bit 0: a 22 output disabled r/w b 7 a23e 0 address a 23 output enable bit 0: a 23 output disabled r/w port function register 4 (pf4bus) bits: 8 , address: 000 8 c1 0 4h bit symbol setting name function r/w b 1 - 0 adrle [1:0] 11 address low - order a9 to a0 output enable bits 11: a9 to a0 output enabled r/w b 2 a10e 1 address a1 0 output enable bit 0: a1 0 output enabled r/w b 3 a11e 1 address a1 1 output enable bit 0: a1 1 output enabled r/w b 4 a12e 1 address a1 2 output enable bit 0: a1 2 output enabled r/w b 5 a13e 1 address a1 3 output enable bit 0: a1 3 output enabled r/w b 6 a14e 1 address a1 4 output enable bit 0: a1 4 output enabled r/w b 7 a15e 0 address a1 5 output enable bit 0: a1 5 output disabled r/w port function register 5 (pf5bus) bits: 8 , address: 000 8 c1 0 5h bit symbol setting name function r/w b 4 dhe 1 data d15 to d8 enable bit 1: pe7 to pe0 set to function as external bus d15 to d8. r/w b 5 dhe32e 0 data d 31 to d 16 enable bit 0: pg7 to pg0 and p97 to p90 set to function as i/o ports. r/w
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 15 of 22 feb 14, 2014 port function register 6 (pf6bus) bits: 8 , address: 000 8 c1 06 h bit symbol setting name function r/w b 4 mdsde 1 sdram pin enable bit see b6 (dqm1e bit) r/w b 6 dqm1e 1 dqm1 output enable bit mdsde dqm1e 11: sdram enabled (all pins) r/w b 7 sdclke 1 sdclk output enable bit 1: sdclk output enabled r/w data register (p0dr) bits: 8 , address: 000 8 c 020 h bit symbol setting name function r/w b2 b2 0 p02 output data stored bit 0: output data = 0 r/w b3 b3 0 p03 output data stored bit 0: output data = 0 r/w data direction register (p0ddr) bits: 8 , address: 0008 c 000 h bit symbol setting name function r/w b2 b2 1 p02 i/o data specification bit 1: output port r/w b3 b3 1 p0 3 i/o data specification bit 1: output port r/w (4) external bus initialization sequence control register (sdicr) bits: 8 , address: 0008 3c 20 h bit symbol setting name function r/w b 0 inirq 1 initialization sequence start bit 1: initialization sequence start r/w sdram initialization register (sdir) bits: 16 , address: 0008 3c 24 h bit symbol setting name function r/w b 3 - b0 arfi[3:0] 0001 initialization auto refresh period bits 0001: 4 cycles r/w b 7 - b4 arfc [3:0] 0010 initialization auto refresh count bits 0010: 2 times r/w b 10 - b8 prc[2:0] 000 initialization precharge cycle count setting bits 000: 3 cycles r/w sdc control register (sdccr) bits: 8 , address: 0008 3c 00 h bit symbol setting name function r/w b 0 exenb 1 operation enable bit 1: operation enable r/w b5 - b4 bsize [1:0] 00 sdram bus width selection bits 00: specifies a 16 - bit bus space r/w sdram mode register (sdmod) bits: 16 , address: 0008 3c 48 h bit symbol setting name function r/w b14 - b 0 mr[14:0] 02 3 0h mode register setting bits executing a write: issues a mode register set command r/w
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 16 of 22 feb 14, 2014 sdram refresh control register (sdrfcr) bits: 16 , address: 000 8 3c 14 h bit symbol setting name function r/w b11 - b 0 rfc[11: 0 ] 2edh a uto refresh required interval setting bits 0010 111 0 11 0 1 : 74 9 cycles r/w b15 - b12 refw [3: 0] 0011 auto refresh cycle/auto refresh release cycle setting bits 00 11 : 4 cycles r/w sdram auto refresh control register (sdrfen) bits: 8 , address: 0008 3c 16h bit symbol setting name function r/w b 0 rfen 1 auto refresh operation enable bit 1: auto refresh operation enable r/w sdc mode register (sdcmod) bits: 8 , address: 0008 3c 01 h bit symbol setting name function r/w b 0 emode 0 endian specification bit 0: the sdram address space endian operation is set to be the same as the operating mode endian setting. r/w sdram access mode register (sdamod) bits: 8 , address: 0008 3c 02 h bit symbol setting name function r/w b 0 be 0 continuous access enable 0: continuous access dis abled r/w sdram address register (sdadr) bits: 8 , address: 0008 3c 40 h bit symbol setting name function r/w b1 - b 0 mxc[1: 0 ] 01 address multiplexing selection bit 01: 9 - bit shift r/w sdram timing register (sdtr) bits: 32 , address: 0008 3c 44 h bit symbol setting name function r/w b2 - b 0 cl[2: 0 ] 011 sdramc column latency setting bits 011: 3 cycles r/w b8 wr 1 write recovery period setting bit 1: 2 cycles r/w b11 - b9 rp[2: 0 ] 000 row precharge period setting bits 000: 1 cycle r/w b1 3 - b 12 r cd [ 1 : 0 ] 00 row column latency setting bits 00: 1 cycle r/w b1 8 - b 16 ras [2: 0 ] 010 row active period setting bits 010: 3 cycles r/w
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 17 of 22 feb 14, 2014 5.5 function descriptions 5.5.1 poweron_reset_pc (1) description the poweron_reset_pc function initializes the stack pointer (sp), and, using embedded functions and standard library functions, sets the interrupt mask bits and sets up uninitialized and initialized data. (2) arguments none (3) return value none (4) flowchart poweron_reset_pc set interrupt table vector (intb) set_intb((unsigned long)__sectop("c$vect")) * 1 call section initialization function _intsct() * 1 set processor status word (psw) set_psw(psw_init) * 1 call main function main() call break function brk() * 1 end set floating point status word (fpsw) set_fpsw(fpsw_init) * 1 call change processor mode function change_psw_pm_to_usermode() * 2 notes: 1. set_intb, set_fpsw, set_psw functions : embedded functions _intsct function : standard library function brk function : embedded function 2. transition from supervisor mode to user mode for details, see the development environment manual listed in section 6, reference documents. figure 7 flow chart ( poweron_reset_pc )
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 18 of 22 feb 14, 2014 5.5.2 main function (1) description the main() function calls the init() and err() functions and performs the program operations (reading and writing memory and comparing the data values). (2) arguments none (3) return value none (4) flowchart main initialize microcontroller init() initialize memory yes no write to memory yes no output ok code (b'0) to p02 pin sdram access address == end address? (sdram area) yes no read data == compare data? call error function err() no yes sdram access address + 1 set sdram access address = start address sdram access address + 1 sdram access address + 1 set sdram access address = start address set sdram access address = start address sdram access address == end address? (sdram area) sdram access address == end address? (sdram area) figure 8 flow chart ( main )
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 19 of 22 feb 14, 2014 5.5.3 init f unction (1) description the init() function initializes the functions used by the microcontroller. (2) arguments none (3) return value none (4) flowchart init end system setup ? set bclk output ? set iclk, bclk, and pclk ? set mode port setup ? set up address output pins (a23-a16) ? set up address output pins (a15-a0) ? set up address bus output pins (a23-a16) ? set up data i/o output pins (d31-d08) ? enable all sdram pins ? set up sdclk output ? set general-purpose ports p03 and p02 data registers to 1 ? set up general-purpose ports p03 and p02 output pins external address space (sdram) setup initialization sequence ? sdram initialization setup ? sdram initialization start ? check sdram status sdram setup ? set sdram bus width ? set mode register ? set up auto refresh ? set sdram endian mode ? set sdram access mode ? set sdram timing ? set sdram address multiplexing start auto refresh ? enable auto refresh enable access ? set sdram to operation enabled wait for 100 s note: a wait time of 100 s is required before sdram initialization due to sdram specifications. figure 9 flow chart ( init )
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 20 of 22 feb 14, 2014 5.5.4 err function (1) description the err() function outputs an error code indicating that a data compare operation found a match failure. (2) arguments none (3) return value none (4) flowchart err output error code (b'0) from p03 pin figure 10 flow chart ( err )
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 21 of 22 feb 14, 2014 6. reference documents user ? s manual: hardware RX62N and rx621 group user ? s manual: hardware rev.1.30 the latest version can be downloaded from the renesas electronics website. user ? s manual: development tools rx family c/c++ compiler package v.1.02 c compiler user ? s manual rev.1.00 the latest version can be downloaded from the renesas electronics website. technical update the latest information can be downloaded from the renesas electronics website.
RX62N group and rx621 group 16- bit sdram connection and access examples r01an0585ej0202 rev.2.02 p age 22 of 22 feb 14, 2014 website and support renesas electronics website http://www.renesas.com/ inquiries http://www.renesas.com/contact/ all trademarks and registered trademarks are the property of their respective owners.
a-1 revision history rev. date description page summary 2.02 feb 14 , 201 4 ? first edition issued
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high - impedance state. in operation with an unused pin in the open - circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot - through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power - on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on - chip power - on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different type number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may di ffer in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system - evaluation test for the given product .
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao rd., putuo district, shanghai, china tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2014 renesas electronics corporation. all rights reserved. colophon 3.0

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